A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays

Author

Desouki, Ahmed S. ; Park, Young-June ; Min, Hong-Shick

Author_Institution

Dept. of Electron. Eng., Seoul Nat. Univ., South Korea

Volume

13

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

471

Lastpage

481

Abstract

Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (I_MOS=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V

Keywords

BiCMOS integrated circuits; circuit layout CAD; doping profiles; 3.3 V; BiCMOS circuit delays; CAD procedure; MOS current; base width; bipolar base doping profile; bipolar devices; device layout; emitter area constraint; horizontal dimensions; load capacitance; optimization procedure; peak base doping concentration; power supply; propagation delay time; vertical doping profile; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Circuit simulation; Delay effects; Doping profiles; Niobium compounds; Power supplies; Propagation delay; Voltage;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.275357

Filename

275357