Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

Author

Diaz, Carlos H. ; Kang, Sung-Mo ; Duvvury, Charvaka

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

13

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

482

Lastpage

493

Abstract

Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIM´s ability to accurately model device behaviour up to the onset of second breakdown

Keywords

MOS integrated circuits; circuit CAD; circuit reliability; digital simulation; electrostatic discharge; failure analysis; impact ionisation; IC reliability; advanced MOS I/O protection devices; advanced MOS process; avalanche breakdown modeling; breakdown phenomenon; circuit-level electrothermal simulator; device behaviour; electrical overstress failures; electrothermal device models; iETSIM; second breakdown; temperature dynamics; Analytical models; Avalanche breakdown; Circuit simulation; Earth Observing System; Electric breakdown; Electrostatic discharge; Electrothermal effects; Protection; Semiconductor process modeling; Thermal stresses;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.275358

Filename

275358