Comparison of one- and two-dimensional models of transistor thermal instability

The IC-VCElocus predicted by a one-dimensional model of thermal instability is compared with the IC-VCElocus predicted by a numerical model which accounts for nonuniform heat generation over the transistor area and also two-dimensional heat flow within the heat sink. Both models include the effects of distributed emitter and base ballast resistance, as well as the magnitude and temperature dependence of current gain. An important result obtained from this comparison is that the I-V loci predicted by the two models are very nearly the same, even though the temperature and power density profiles over the transistor die are distinctly different. It is the I-V locus which is of most practical interest, since it is one portion of the boundary of the forward safe operating area (SOA). The similarity of the I-V loci should allow one to use the simple one-dimensional model to predict a particular SOA, even though the assumptions under which the model was originally derived are not valid at the onset of thermal instability. Confirmation of this approach has been obtained by demonstrating good agreement between the measured safe operating area and that predicted by the one-dimensional model for both single- and double-diffused transistors. The predicted improvement due to the addition of discrete emitter resistors has also been verified by SOA measurements on actual devices. The device parameters which are important in determining SOA are the effective emitter and base resistances, the magnitude and temperature dependence of current gain, and the effective thermal resistance between the active region of the transistor and its heat sink. The quantitative dependence of SOA due to each of these parameters is described.