DocumentCode :
1048555
Title :
Interlevel dielectric failures in copper/low-k structures
Author :
Alers, Glenn B. ; Jow, K. ; Shaviv, R. ; Kooi, Gerrit ; Ray, G.W.
Author_Institution :
Novellus Syst., San Jose, CA, USA
Volume :
4
Issue :
2
fYear :
2004
fDate :
6/1/2004 12:00:00 AM
Firstpage :
148
Lastpage :
152
Abstract :
Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.
Keywords :
copper; cracks; dielectric properties; diffusion barriers; failure (mechanical); materials testing; bias-temperature stress; constant voltage tests; copper diffusion; copper extrusion; crack formation; dielectric barrier; dielectric diffusion barriers; dielectric layers; electrostatic force; failure modes; interfacial adhesion strengths; interlevel dielectric failures; low-k interface; low-k structures; mechanical cracking; ramped voltage tests; Breakdown voltage; Copper; Dielectric breakdown; Dielectric materials; Extrapolation; Failure analysis; Life estimation; Life testing; Silicon compounds; Stress; Adhesion; BTS; bias-temperature stress; copper; dielectric; low k;
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2004.831989
Filename :
1318618
Link To Document :
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