Title :
CMOS IC technology scaling and its impact on burn-in
Author :
Vassighi, Arman ; Semenov, Oleg ; Sachdev, Manoj ; Keshavarzi, Ali ; Hawkins, Chuck
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada
fDate :
6/1/2004 12:00:00 AM
Abstract :
This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures. Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss of good parts during burn-in. The paper discusses the effect of junction temperature on device reliability, aging, and burn-in procedure optimization. The effect of device thermal runaway and the requirements it forces on commercial burn-in ovens, device package, and device cooling are also described.
Keywords :
CMOS integrated circuits; cooling; integrated circuit packaging; integrated circuit reliability; leakage currents; thermal management (packaging); CMOS IC technology scaling; burn-in procedure optimization; commercial burn-in ovens; device cooling; device package; device reliability; device thermal runaway; junction temperatures; leakage currents; semiconductor burn-in; thermal management; yield loss; CMOS integrated circuits; CMOS technology; Leakage current; Microprocessors; Packaging; Paper technology; Temperature; Thermal resistance; Thermal stresses; Voltage; Burn-in; junction temperature; packaging; reliability; technology scaling; thermal management;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2004.826591