Power minimization for dynamic PLAs

Dynamic programmable logic arrays (PLAs) which are built of the nor-nor structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the nor-nor structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the nand functionality on top of the nor structure, thus, lowering the switching activities in the product lines, as well as power consumption. Since there are many candidates for super product lines, we have developed a computer-aided design (CAD) algorithm based on the maximum weighted matching to find the optimal solution. We have performed experiments on a large set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. The post simulation results show significant reduction in power consumption. Among the experimental circuits, circuit alu3 has the highest power saving 62.9% with the delay overhead 5.4%, and circuit newpla2 has the lowest power saving with delay overhead 22.7%. In addition, circuit in4 improves the delay with 5.7%. On the average, the power consumption can be saved 55.8% and the delay overhead is merely 3.3% for 25 circuits