Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End

Author

Rajaee, O. ; Un-Ku Moon

Author_Institution

Qualcomm Inc., San Diego, CA, USA

Volume

48

Issue

2

fYear

2013

fDate

Feb. 2013

Firstpage

502

Lastpage

515

Abstract

A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18- μm CMOS, the ADC achieves 12 ENOB with 64-MHz clock at 6× OSR while using only a 9-b linear front-end multiplying DAC. The delta-sigma sub-ADCs dissipate 400 μW of extra power (out of 13.9-mW total power) while significantly enhancing the overall ADC linearity.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit feedback; delta-sigma modulation; CMOS process; analog imperfections; delta-sigma subADC; frequency 64 MHz; high-order noise shaping; highly linear noise-shaped pipelined ADC; linear front-end multiplying DAC; minimal complexity ΔΣ modulator; power 13.9 mW; power 400 muW; relaxed accuracy front-end; residue feedback; size 0.18 mum; Accuracy; Finite impulse response filter; Gain; Modulation; Noise; Noise shaping; Quantization; $Delta Sigma$ modulation; feedback DAC; loop filter; noise shaping; oversampling converters; pipelined ADCs; switched-capacitor circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2227605

Filename

6392910