DocumentCode :
1049061
Title :
DSM interconnects: importance of inductance effects and corresponding range of length
Author :
Deschacht, D.
Author_Institution :
Lab. d´´Inf., de Robotique et de Microelectron., UMR CNRS, Montpellier
Volume :
14
Issue :
7
fYear :
2006
fDate :
7/1/2006 12:00:00 AM
Firstpage :
777
Lastpage :
779
Abstract :
To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-mum technology
Keywords :
inductance; integrated circuit interconnections; integrated circuit modelling; system-on-chip; transmission lines; 0.18 micron; DSM interconnects; RC model; RLC model; fall time; inductance effect; interconnection length; on-chip interconnections; rise time; transmission lines; Distributed parameter circuits; Impedance; Inductance; Integrated circuit interconnections; Microprocessors; RLC circuits; System-on-a-chip; Transmission line theory; Transmission lines; Very large scale integration; Electromagnetic analysis; inductance effect; interconnection length; on-chip interconnections; transmission lines;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2006.878347
Filename :
1661626
Link To Document :
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