The read-write disturb problem in plated wire memories

Data illustrating the read-write disturb problem in plated wire memories are reported. It is shown that the application of a dc hard axis field of the order of 1 Oe acting in the same direction as the word pulse can alleviate the disturb. Read-write disturb threshold curves are presented for a variety of pulse sequences incorporating either unipolar or bipolar bit currents. It is found that the second pulse of a bipolar disturb bit current is, for long pulse widths, the most influential. A model, which is based upon an extension of the modified lever mechanism used to explain conventional creep, is proposed. This model can explain all the data. In addition, it predicts that as the bit pulse length is decreased, the bipolar disturb sequence should become less severe. This is observed and, for a pulse width of 50 ns, the disturb threshold moves well above the wall motion current. Finally, a number of methods for increasing operating margins is presented.