• DocumentCode
    1049210
  • Title

    Low-leakage n- and p-channel Silicon-gate FET´s with an SiO2-Si3N4-gate insulator

  • Author

    Dockerty, Robert C. ; Abbas, Shakir A. ; Barile, Conrad A.

  • Author_Institution
    IBM, Systems Products Division, Hopewell Junction, N. Y.
  • Volume
    22
  • Issue
    2
  • fYear
    1975
  • fDate
    2/1/1975 12:00:00 AM
  • Firstpage
    33
  • Lastpage
    39
  • Abstract
    n-channel and p-channel silicon-gate FET´s are fabricated using a 300-Å SiO2-300-Å Si3N4gate insulator. These devices have low leakage and are suitable for dynamic FET-memory applications. Very low n-channel leakage is achieved by using an n- or p-doped polycrystalline-silicon field shield. One-device dynamic memory cells exhibit long average retention times: 158 s for the n-channel cell and 34 s for the p-channel cell. An oxygen or steam anneal of the Si3N4is necessary to prevent a large Vtshift during bias-temperature stress.
  • Keywords
    Annealing; Capacitance; Circuits; Dielectric substrates; FETs; Insulation; Silicon; Stress; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1975.18072
  • Filename
    1477907