Improved Thermal Performance of SOI Using a Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO₂, polycrystalline silicon (polysilicon), and SiO₂. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO₂. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO₂ buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO₂ BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.