Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Author

van Dal, M.J.H. ; Boccardi, G. ; Veloso, A. ; Locorotondo, S. ; Shi, X. ; Demeurisse, C. ; Vrancken, C. ; Verbeeck, R. ; Lauwers, A. ; Kittl, J.A.

Author_Institution

Philips Res. Eur., Leuven

Volume

27

Issue

8

fYear

2006

Firstpage

665

Lastpage

667

Abstract

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt₂Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ~ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni₃₁Si₁₂) pMOSFET devices. A low threshold voltage les|-0.29 V| was obtained for the Pt₂Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt₂Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON

Keywords

MOSFET; hafnium compounds; nickel compounds; platinum compounds; silicon compounds; 0.29 V; 60 nm; FUSI; HfSiON; NiSi; Pt₂Si; full silicidation; low threshold voltage; pMOSFET devices; Capacitors; Dielectrics; MOSFETs; Microelectronics; Platinum; Scalability; Silicidation; Silicides; Threshold voltage; Wet etching; Full silicidation (FUSI); HfSiON dielectric; NiSi; PtSi; SiON dielectric; high-; metal gate; threshold voltage; work function;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2006.878051

Filename

1661724