An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

Author

Miles, Lowell H. ; Gambles, Jody W. ; Maki, Gary K. ; Ryan, William E. ; Whitaker, Sterling R.

Author_Institution

Center for Microelectron. & Biomolecular Res., Univ. of Idaho, Idaho Falls, ID

Volume

41

Issue

8

fYear

2006

Firstpage

1686

Lastpage

1691

Abstract

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-mum CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two-stage encoder requires 8176 flip-flops

Keywords

CMOS integrated circuits; encoding; flip-flops; parity check codes; polynomials; 0.25 micron; 21 bit; 860 Mbit/s; CMOS process; LDPC code; Shannon limit; flip-flops; functional sharing; generator polynomial reconstruction; look-ahead scheme; low-density parity-check codes; low-density parity-check encoder; parity register; partial product multiplication; two-stage encoder; CMOS process; Character generation; Data communication; Decoding; Error correction codes; Flip-flops; Linear code; Parity check codes; Polynomials; Throughput; Error correction; LDPC; cyclic codes; encoding; quasi-cyclic codes;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.877253

Filename

1661745