A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

Author

Anders, Mark A. ; Mathew, Sanu K. ; Hsu, Steven K. ; Krishnamurthy, Ram K. ; Borkar, Shekhar

Author_Institution

Intel Corp., Hillsboro

Volume

43

Issue

1

fYear

2008

Firstpage

214

Lastpage

222

Abstract

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 V_t 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.

Keywords

CMOS integrated circuits; Viterbi decoding; field effect MMIC; CMOS technology; Radix-4 ripple-carry ACS circuits; bit rate 1.9 Gbit/s; frequency 3.8 GHz; power 358 mW; programmable ring-buffer decoders; reconfigurable path metric read/write control; size 90 nm; state reconfigurable Viterbi accelerator; temperature 50 degC; tree-bitline traceback memory circuits; voltage 1.3 V; CMOS technology; Circuits; Convolutional codes; Maximum likelihood decoding; Power generation; Power measurement; Read-write memory; Signal processing algorithms; Throughput; Viterbi algorithm; Convolutional codes; Viterbi; reconfigurable; signal processing; sleep transistor; wireless;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.909336

Filename

4443180