Title :
Multilevel logic minimization using K-map XOR patterns
Author :
Tinder, Richard F.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
Entered variable XOR patterns are used in compressed Karnaugh maps to achieve gate-level minimum functions not possible with standard SOP and POS forms. Procedures are given for minimum cover extraction and verification. The design of a simple ALU illustrates multilevel-multiple output optimization
Keywords :
logic design; logic gates; minimisation; minimisation of switching nets; multivalued logic; ALU design; K-map XOR patterns; compressed Karnaugh maps; entered variable XOR patterns; gate-level minimum functions; minimum cover extraction; minimum cover verification; multilevel logic minimization; multilevel-multiple output optimization; Algebra; CMOS logic circuits; CMOS technology; Delay; Design optimization; Hardware; Joining processes; Logic devices; Logic functions; Minimization methods;
Journal_Title :
Education, IEEE Transactions on
