Title :
A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface
Author :
Villa, Corrado ; Vimercati, Daniele ; Schippers, Stefan ; Polizzi, Salvatore ; Scavuzzo, Andrea ; Perroni, Maurizio ; Gaibotti, Maurizio ; Sali, Mauro Luigi
Author_Institution :
ST Microelectron., Agrate Brianza
Abstract :
This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.
Keywords :
CMOS memory circuits; flash memories; DDR interface; NOR flash memory; byte rate 2.25 MByte/s; byte rate 400 MByte/s; program throughput; read throughput; size 65 nm; storage capacity 1 Gbit; time 70 ns; time-domain voltage-ramp reading concept; voltage 1.8 V; Clocks; Data structures; Flash memory; Hardware; Operational amplifiers; Paper technology; Throughput; Time domain analysis; Voltage; Wireless communication; DDR interface; NOR flash memory; multilevel flash;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.916028
