Title :
Higher Order Autocorrelation Vision Chip
Author :
Ishii, Daku ; Yamamoto, Kenkichi ; Kubozono, Munehiro
Author_Institution :
Hiroshima Univ.
Abstract :
This paper describes very large scale integration implementation using a new vision chip architecture specialized for target tracking and recognition. A 64 times 64 pixel prototype vision chip and its evaluation results are shown. The extraction algorithms of both higher order local autocorrelation (HLAC) features and moment features are implemented on the prototype chip in order to achieve high-speed image processing and enhanced pixel integration. The chip is integrated on a 5.00 mm times 5.00 mm chip using a 0.35-mum CMOS DLP/TLM process; the pixel size is 44.2 mumtimes48.3 mum. The maximum current consumption is approximately 400 mA, and the chip can calculate all HLAC features more than 26 times in 1 ms. The experimental results also demonstrate that the chip can successfully recognize and count high-speed objects at real time
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; correlation methods; digital signal processing chips; object recognition; target tracking; transmission line matrix methods; 0.35 micron; 400 mA; CMOS DLP-TLM process; HLAC feature; counting objects; extraction algorithms; high-speed image processing; higher order autocorrelation vision chip; integrated architecture; moment features; pixel integration; target recognition; target tracking; very large scale integration; Algorithm design and analysis; Autocorrelation; Cities and towns; Image processing; Machine vision; Pixel; Prototypes; Target recognition; Target tracking; Very large scale integration; Counting objects; higher order local autocorrelation (HLAC); integrated architecture; moment features; target recognition; vision chip;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.878024