Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n⁺drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n⁺region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.