New Superjunction LDMOST With N-Buffer Layer

Author

Park, Il-Yong ; Salama, C. Andre T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.

Volume

53

Issue

8

fYear

2006

Firstpage

1909

Lastpage

1913

Abstract

A buffered superjunction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is proposed and the experimental implementation in a CMOS technology are presented. The proposed structure uses an N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer, and the P-substrate. The practical implementation involves the additional formation of the N-buffer and the pillars in a 0.8-mum CMOS process. Both of the simulation and the experimental results confirm that the substrate effects are suppressed by the buffered structure

Keywords

buffer layers; power MOSFET; 0.8 micron; CMOS compatible process; CMOS technology; SJ-LDMOST structure; buffered structure; n-buffer layer; power MOSFET; shallow pillar height; substrate effects; substrate-assisted depletion effects; superjunction LDMOST; Breakdown voltage; CMOS technology; Councils; Degradation; MOSFET circuits; Power MOSFET; Power engineering and energy; Semiconductor device doping; Space charge; Substrates; CMOS compatible process; N-buffer layer; lateral; power MOSFET; shallow pillar height; substrate-assisted depletion effects; superjunction (SJ);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.877007

Filename

1661894