A new class of optimal bounded-degree VLSI sorting networks

Minimum-area very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log,N ) time. However, most of such networks proposed have complex structures, and no explicit network construction is given in others. New designs of optimal VLSI sorters that combine rotate-sort with enumeration-sort to sort N numbers, each of length w (1+∈)logN bits (for any constant ∈>0), in time T∈[Ω(logN), Θ√(NlogN)]. The main attributes of the proposed sorters are a significantly smaller number of sorting nodes than in previous designs and smaller constant factors in their time complexity. The proposed sorters use a new class of reduced-area K -shuffle layouts to route data between sorting stages. These layouts can be also used to provide explicit designs for the column-sort technique developed by F.T. Leighton (1985)