Comparison of DMOS/IGBT-compatible high-voltage termination structures and passivation techniques

Author

Korec, Jacek ; Held, Raban

Author_Institution

Daimler-Benz Res. Inst., Frankfurt, Germany

Volume

40

Issue

10

fYear

1993

fDate

10/1/1993 12:00:00 AM

Firstpage

1845

Lastpage

1854

Abstract

Single and multiple field plates are considered in conjunction with field-limiting rings and junction terminal extension (JTE) junction terminations with and without an additional SIPOS passivation. This comparison is done for shallow p-n junctions on n-type substrates doped to 1-2×10¹⁴ cm^-3 for 500- or 1000-V devices, respectively. The conclusions obtained from two-dimensional numerical simulations are checked experimentally. The best results have been obtained using a JTE structure with SIPOS passivation

Keywords

MOS integrated circuits; insulated gate bipolar transistors; integrated circuit technology; passivation; power integrated circuits; power transistors; 1000 V; 500 V; DMOS compatible structures; HVIC; SIPOS passivation; field-limiting rings; high-voltage termination structures; junction terminal extension; junction terminations; multiple field plates; n-type substrates; passivation techniques; shallow p-n junctions; single field plates; two-dimensional numerical simulations; Helium; Insulated gate bipolar transistors; Insulation; Numerical simulation; P-n junctions; Passivation; Protection; Semiconductor films; Silicon; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.277343

Filename

277343