DocumentCode :
1052893
Title :
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering
Author :
El-Maleh, A. ; Khursheed, S.
Author_Institution :
King Fahd Univ. of Pet. & Miner., Dhahran
Volume :
1
Issue :
4
fYear :
2007
fDate :
7/1/2007 12:00:00 AM
Firstpage :
364
Lastpage :
368
Abstract :
Test compaction is an effective technique for reducing test data volume and test application time. The authors present a new static test compaction technique based on test vector decomposition and clustering. Test vectors are decomposed and clustered for faults in an increasing order of faults detection count. This clustering order gives more degree of freedom and results in better compaction. Experimental results demonstrate the effectiveness of the proposed approach in achieving higher compaction in a much more efficient CPU time than the previous clustering-based test compaction approaches.
Keywords :
circuit testing; combinational circuits; CPU time; clustering-based test compaction; combinational circuits; fault detection count-directed clustering; static test compaction; test application time reduction; test data volume reduction; test vector clustering; test vector decomposition;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt:20070004
Filename :
4271379
Link To Document :
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