Title :
A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 μm CMOS Technology
Author :
Kim, Byung-Guk ; Kim, Lee-Sup ; Byun, Sangjin ; Yu, Hyun-Kyu
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Daejeon
Abstract :
In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mum process consumes 210 mW from 1.2 V logic supply.
Keywords :
CMOS integrated circuits; delay lock loops; dividing circuits; system-on-chip; CMOS technology; DEMUX; buffer insertion; delay-locked loop; low power consumption; low-power divide-by-2 circuit; power 210 mW; shared current source; signal bandwidth; size 0.13 micron; static frequency divider; test chip; voltage 1.2 V; Bandwidth; CMOS technology; Coupling circuits; Delay; Energy consumption; Frequency conversion; Inductors; Latches; Logic testing; Timing; CMOS; DEMUX; delay-locked loop (DLL); latch; static frequency divider;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.914332
