On the proportioning of chip area for multistage Darlington power transistors

A Model has been proposed and solved in which all Darlington circuits may be represented to a first order approximation by five constants, one of which may be normalized. Experimental verification has been provided offering excellent agreement with theory. Several orders of magnitude improvement in current-handling ability have been shown to exist for multistage Darlington circuits over conventional discrete transistors. The allocation of chip area for each stage is extensively discussed as a design aid.