DocumentCode :
1053712
Title :
A technique for optimizing the design of power semiconductor devices
Author :
Schlegel, E.S.
Volume :
23
Issue :
8
fYear :
1976
fDate :
8/1/1976 12:00:00 AM
Firstpage :
924
Lastpage :
927
Abstract :
A technique is described that provides a basis for predicting whether any device design change will improve or degrade the unavoidable trade-off that must be made between the conduction loss and the turn-off speed of fast-switching high-power thyristors. The technique makes use of a previously reported method by which, for a given design, this trade-off was determined for a wide range of carrier lifetimes. It is shown that by extending this technique, one can predict how other design variables affect this trade-off. The results show that for relatively slow devices the design can be changed to decrease the current gains to improve the turn-off time without significantly degrading the losses. On the other hand, for devices having fast turn-off times design changes can be made to increase the current gain to decrease the losses without a proportionate increase in the turn-off time. Physical explanations for these results are proposed.
Keywords :
Cathodes; Charge carrier lifetime; Degradation; Design optimization; Frequency; Power semiconductor devices; Shape; Solid state circuits; Temperature; Thyristors;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1976.18510
Filename :
1478523
Link To Document :
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