A VMEbus clock system for accelerator control

Two VMEbus modules have been designed to generate and receive a clock signal. Together they implement a clock system which can generate timing markers with 200-ns resolution and can generate timing delays of over 1 h with 1-μs resolution. The clock generator module contains both a time line generator programmed to produce clock events at specific times and eight programmable input channels to produce clock events when externally triggered. Additional clock events are generated directly from the VMEbus. Generators can be cascaded for added capability. The clock timer module receives the signal from the generator. It can be programmed to recognized specific clock events which act as triggers to the eight timing channels on the module