Title :
ID– VGS-Based Tools to Profile Charge Distributions on NROM Memory Devices
Author :
Padovani, Andrea ; Larcher, Luca ; Pavan, Paolo ; Avital, Lior ; Bloom, Ilan ; Eitan, Boaz
Author_Institution :
Univ. di Ferrara, Ferrara
fDate :
3/1/2007 12:00:00 AM
Abstract :
NROM memory cells are proposed as promising nonvolatile memories. Even though these devices should have a better endurance than their floating-gate counterparts, issues have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge-trapping material. Thus, a deep knowledge of charge distribution features is crucial for program/erase bias optimization, reliability predictions, and future scaling. In this paper, we will introduce and discuss two tools based on ID-VGS curves (i.e., subthreshold slope and ID temperature effects) which will be used to profile charge distribution. Simple formulas allowing to calculate charge distribution length and density will be derived, and their accuracy will be tested for cells programmed at different levels and under different bias conditions. Finally, we will discuss the limits of both tools when applied to erased NROM cells, i.e., cells having both electron and hole distributions in the nitride region above the junction.
Keywords :
flash memories; optimisation; semiconductor device models; semiconductor device reliability; semiconductor storage; ID-VGS -based tools; NROM memory devices; charge density; charge distribution length calculation; charge distribution profile; charge-trapping material; device simulations; electron distributions; erased NROM cells; flash memory; gate-induced drain leakage; hole distributions; nitride-based trapping storage; nonvolatile memories; program-erase bias optimization; semiconductor device reliability; semiconductor memory cell; trapped charge profiling; Charge carrier processes; Current measurement; Electron traps; Flash memory; MOSFET circuits; Nonvolatile memory; Read only memory; Semiconductor device reliability; Temperature distribution; Testing; Device simulations; Flash memory; NROM; gate-induced drain leakage (GIDL); nitride-based trapping storage; semiconductor device reliability; trapped charge profiling;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2007.897528