Title :
A hardened technology on SOI for analog devices
Author :
Dupont-Nivet, E. ; Delagnes, E. ; Leray, J.L. ; Martin, J.-L. ; Montaron, J. ; Blanc, J.P. ; Delevoye, E. ; Gauthier, J. ; De Pontcharra, J. ; Truche, R. ; Beuville, E. ; Dentan, M. ; Fourches, N.
Author_Institution :
CEA, Centre d´´Etudes de Bruyeres-Le-Chatel, France
fDate :
6/1/1992 12:00:00 AM
Abstract :
A hardened and mixed analog-digital technology under development is presented. This technology currently includes a PJFET with a good hardness and CMOS transistors with a potential multi-megarad hardness. First tests of bipolar transistors with a not yet optimized structure (structure of the JFET) are discussed. The feasibility of a PJFET with a 1.2-μm-thick active layer on top of a SIMOX wafer with a very good immunity to radiation has been shown. A highly doped buried layer has been successfully introduced into the process, even if some spreading of that layer must be taken into account to adjust the threshold voltages. This buried layer is able to screen any charge in the buried oxide from the active layer even after several tens of megarads. The neutron analysis of nonoptimized bipolar transistors gives confidence in the achievement of good quality and hardened transistors
Keywords :
application specific integrated circuits; bipolar transistors; insulated gate field effect transistors; junction gate field effect transistors; linear integrated circuits; monolithic integrated circuits; neutron effects; radiation hardening (electronics); 1.2 micron; CMOS transistors; PJFET; SIMOX wafer; Si-SiO2-Si; analog devices; bipolar transistors; doped buried layer; hardened technology; immunity to radiation; mixed analog-digital technology; neutron analysis; Analog-digital conversion; CMOS technology; Detectors; Electronic equipment testing; Elementary particles; Immunity testing; Large Hadron Collider; Neutrons; Physics; Transistors;
Journal_Title :
Nuclear Science, IEEE Transactions on
