Title :
Single event upset error propagation between interconnected VLSI logic devices
Author_Institution :
Control Data Corp., Minneapolis, MN, USA
fDate :
6/1/1992 12:00:00 AM
Abstract :
The author presents experimental and analytical results of single event upset error propagation between interconnected VLSI logic devices representative of a spaceborne system. The results show that up to 50% of the time a single transistor upset internal to a logic device can result in system failure. The experimental testing has verified error propagation between interconnected VLSI devices. The data show that by neglecting the propagated errors an overly low combined error rate may be calculated at the system level. Catastrophic system-level failures were observed with occurrence frequencies between 0.2 failures/million ion/cm2 and 1.2 failures/million ions/cm2, verifying upset propagation to system output with implications of error multiplication either within individual devices or as an error propagates through the system
Keywords :
VLSI; aerospace instrumentation; integrated logic circuits; ion beam effects; reliability; SEV error propagation; analytical results; catastrophic failures; error multiplication; experimental testing; failure rate; interconnected VLSI logic devices; single event upset error propagation; single transistor upset; spaceborne system; system failure; system-level failures; upset propagation; Central Processing Unit; Clocks; Cyclotrons; Error correction; Logic devices; Performance evaluation; Single event upset; Space vehicles; Testing; Very large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
