Title :
10 bit 200 MS/s CMOS D/A converter employing high-speed limiter
Author :
Lee, Seung-Chul ; Cho, Min-Hyung ; Hyun-Kyu Yoo
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejon, South Korea
fDate :
11/7/2002 12:00:00 AM
Abstract :
A 10 bit 200 MS/s CMOS current-steering digital-to-analogue converter (DAC) employing a new voltage limiter to reduce the feedthrough of the control signals is presented. For high-speed operation of the limiter, a design technique based on the parasitic capacitor of a PMOS transistor is proposed. At 200 MS/s, a spurious-free dynamic range of 65 dBc for a 40 MHz output signal has been achieved from the proposed DAC.
Keywords :
CMOS integrated circuits; digital-analogue conversion; high-speed integrated circuits; integrated circuit design; limiters; 0.35 micron; 40 MHz; CMOS current-steering digital-to-analogue converter; PMOS transistor parasitic capacitor; control signal feedthrough; current-cell driver; design technique; high-speed limiter; high-speed operation; spurious-free dynamic range;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20021013
