DocumentCode :
1054572
Title :
MB-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design
Author :
Lee, Hsun-Cheng ; Chang, Yao-Wen ; Yang, Hannah Honghua
Author_Institution :
Synopsys, Taipei
Volume :
26
Issue :
8
fYear :
2007
Firstpage :
1430
Lastpage :
1444
Abstract :
In this paper, we present an agglomeratively multilevel floorplanning/placement framework based on the B -tree representation called MB- tree to handle the floorplanning and packing for large-scale building modules. The MB-tree adopts a two-stage technique, i.e., clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B -tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB-tree preserves the geometric relations among modules during declustering, which makes the MB-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, the MB-tree scales very well as the circuit size increases.
Keywords :
circuit optimisation; integrated circuit layout; simulated annealing; trees (mathematics); B -tree representation; MB*-tree; area utilization; declustering stage; geometric relations; large-scale building-module design; module connectivity; multilevel floorplanning; multilevel placement; simulated annealing; Buildings; Circuits; Costs; Data structures; Design automation; Design optimization; Large-scale systems; Optimized production technology; Silicon; Simulated annealing; Floorplanning; layout; multilevel framework; physical design; placement;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2007.891368
Filename :
4271553
Link To Document :
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