Evaluation of transistor property variations within chips on 300-mm wafers using a new MOSFET array test structure

A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and across a 300-mm wafer. The evaluation system was established with a conventional parametric tester and dc power supplies suitable for application on production lines. It was observed that threshold voltage (V_th) variations increased with the reduction of the channel area. A difference was also observed in the standard deviation (σ_vt) between NMOS and PMOS. From statistical evaluations, controlling CDs and improving rolloff characteristics were found to be important to reduce V_th variations.