Title :
Truncated ternary multipliers
Author :
Parhami, Behrooz
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, Santa Barbara, CA, USA
Abstract :
Balanced ternary number representation and arithmetic, based on the symmetric radix-3 digit set {-1, 0, +1}, has been studied at various times in the history of computing. Among established advantages of balanced ternary arithmetic are representational symmetry, favourable error characteristics and rounding by truncation. In this study, we show an additional advantage: that of lower-error truncated multiplication with the same relative cost reduction as in truncated binary multipliers.
Keywords :
digital arithmetic; multiplying circuits; balanced ternary arithmetic; balanced ternary number representation; cost reduction; favourable error characteristics; lower-error truncated multiplication; representational symmetry; symmetric radix-3 digit set; truncated binary multiplier; truncated ternary multipliers; truncation;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt.2013.0133