Title :
Realizable Reduction of RC Networks
Author :
Sheehan, Bernard N.
Author_Institution :
Mentor Graphics Corp., Wilsonville
Abstract :
In this paper, we develop from various points of view the time-constant equilibration reduction (TICER) algorithm, a circuit-reduction method that converts a given network into a smaller network (one with fewer nodes and branches) by eliminating nodes that have few neighbors and small nodal time constants. Advantages of TICER include: great efficiency, intuitive error control, preservation of sparsity, output in the form of an network, and the ability to handle networks with many ports.
Keywords :
RC circuits; integrated circuit interconnections; integrated circuit modelling; RC networks; intuitive error control; time-constant equilibration reduction; Control systems; Differential equations; Error correction; Integrated circuit interconnections; LAN interconnection; Poles and zeros; Radio control; Robustness; Systems engineering and theory; Voltage control; Interconnect modeling; model-order reduction (MOR); parasitic extraction; time-constant equilibration reduction (TICER);
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2007.891374
