Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms

Two approaches to handling the computational requirements of computer-aided design problems are considered. One approach is to take advantage of the hierarchical nature of circuit design and develop hierarchical CAD algorithms. Another involves the use of parallel processing and development of parallel CAD algorithms. How these two approaches can be combined to speed up various CAD applications is discussed. Toward this goal, two general problems in scheduling are solved: parallelizable independent task scheduling (PITS) and parallelizable dependent task scheduling (PDTS). The PITS scheduling theory is applied to a parallel hierarchical circuit extractor, and the PDTS scheduling theory is applied to a parallel hierarchical global router. Both implementations show speedups of about six on eight processors of a shared-memory multiprocessor