DocumentCode :
1054778
Title :
Standard cell layout with regular contact placement
Author :
Wang, Jun ; Wong, Alfred K. ; Lam, Edmund Y.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, China
Volume :
17
Issue :
3
fYear :
2004
Firstpage :
375
Lastpage :
383
Abstract :
The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.
Keywords :
FIR filters; MOSFET; Viterbi decoding; application specific integrated circuits; cellular arrays; combinational circuits; electrical contacts; integrated circuit layout; lithography; 250 nm; Viterbi decoder; add-compare-select unit; finite-impulse-response filter; grid pitch; regular contact placement; resolution enhancement technologies; shrinking; standard cell layout; Apertures; Circuits; Finite impulse response filter; High speed optical techniques; Image quality; Lighting; Lithography; Optical filters; Optical imaging; Viterbi algorithm; Double exposure; RETs; fabrication-friendly layout; low $k_1$ lithography; regularly placed contact; standard cells;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2004.831522
Filename :
1321135
Link To Document :
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