On optimizing VLSI testing for product quality using die-yield prediction

An adaptive testing procedure that uses spatial defect clustering information and the available test results for neighboring dies to optimize test costs for VLSI testing is proposed. For the same average test costs, the approach shows the potential for better than a factor-of-two improvement in average defect levels. Perhaps more significantly, it allows the separation of high-quality circuits with defect levels more than order of magnitude better than the average for the production run. The proposal is orthogonal to all other approaches for improving defect levels and can be combined with them