DocumentCode
1054875
Title
Functional synthesis of digital systems with TASS
Author
Amellal, Said ; Kaminska, Bozena
Author_Institution
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Volume
13
Issue
5
fYear
1994
fDate
5/1/1994 12:00:00 AM
Firstpage
537
Lastpage
552
Abstract
Synthesizing a digital system from a functional description is a complex process requiring the solution of various different problems. TASS (Tabu Search Synthesis System) is a functional synthesis system made up of interdependent modules based on new and more efficient algorithms. First, a control and data flow graph model for system representation is developed and presented. This model generates a single graph representing both the data and control flows of a VHDL behavioral description. A new representation of conditional branches and a mutual exclusion testing procedure offering optimized resource sharing and critical path reduction possibilities have been developed. This graph model is an environment used for various synthesis needs starting from high-level transformations to FSM synthesis for controller implementation. A new mathematical formulation of the scheduling problem is developed using a new approach based on penalty weights. This approach avoids the inflexibility of the ILP formulations developed in related works where the functional unit performing each type of operation is fixed prior to scheduling. The Tabu Search technique, which has been effective in finding optimal solutions for many types of large and difficult combinatorial optimization problems, has been adapted for this purpose. This technique, which performs an intelligent and fast solution space exploration, combined with an effective mathematical formulation makes the scheduling algorithm presented here very powerful
Keywords
finite state machines; graph theory; logic CAD; logic circuits; scheduling; specification languages; FSM synthesis; TASS; Tabu Search Synthesis System; VHDL behavioral description; combinatorial optimization problems; conditional branches; control flow; critical path reduction; data flow graph model; digital system synthesis; functional synthesis; high-level transformations; interdependent modules; mutual exclusion testing procedure; optimized resource sharing; penalty weights; scheduling problem; Control system synthesis; Digital systems; Flow graphs; Hardware design languages; High level synthesis; Multiplexing; Registers; Resource management; Space exploration; Testing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.277628
Filename
277628
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