Identification of redundant delay faults

Various defects during fabrication have been shown in the literature to introduce delay faults in logic circuits. This paper analyzes the effects of these defects on the normal operation of logic circuits with the goal of developing an appropriate model for these faults. Single and multiple delay faults in this model are analyzed to determine if they are redundant with respect to the normal operation of the logic circuit. The relationships between delay redundancies and stuck-at redundancies are discussed. The redundancy identification techniques are applied to various benchmarks circuits and experimental data are presented