Optimization of state encoding in distributed circuits

Delay-insensitive (DI) circuits are a class of asynchronous circuit whose functional correctness is unaffected by component delays or wire delays. DI circuits can be considered as distributed circuits in which the system is protocol based and no global information is available. Existing truly DI implementations of state machines have so far required area which is linearly proportional to the number of states in the machine and have not yet applied the technique of state encoding which exists in synchronous design. We introduce an optimization/synthesis technique for DI sequence generators which uses implicit state encoding. An interesting result is proved: modulo-N counters using O(log N) area require only an average case time complexity of O(1)