Title :
Satisfaction of input and output encoding constraints
Author :
Saldanha, Alexander ; Villa, Tiziano ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
5/1/1994 12:00:00 AM
Abstract :
Three encoding problems relevant to the synthesis of digital circuits are input, output, and state encoding. Several encoding strategies have been proposed in the past that decompose the encoding problem into a two step process of constraint generation and constraint satisfaction. The latter requires the assignment of binary codes to symbols subject to the satisfaction of constraints on the codes. This paper focuses on the constraint satisfaction problem. We prove that constraint satisfaction is NP-complete. We develop a framework for the satisfaction of both input and output encoding constraints, and describe a polynomial time (in the number of symbols to be encoded) algorithm to check for the existence of a solution for a set of input and output constraints. An exact algorithm to determine the minimum number of encoding bits required to satisfy all the given constraints is provided, and a heuristic algorithm is also described. The application of this framework to a variety of encoding problems with different cost functions is illustrated. Experimental results on standard benchmarks are given for the exact and heuristic algorithms
Keywords :
computational complexity; encoding; logic design; NP-complete; constraint satisfaction; cost functions; digital circuit synthesis; heuristic algorithm; input encoding constraints; logic synthesis; output encoding constraints; polynomial time algorithm; Binary codes; Circuit synthesis; Cost function; Digital circuits; Encoding; Heuristic algorithms; Laboratories; Logic; Minimization; Polynomials;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on