VLSI architecture for a flexible block matching processor

Author

De Vos, Luc ; Schöbinger, Matthias

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

Volume

5

Issue

5

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

417

Lastpage

428

Abstract

A flexible and powerful VLSI architecture for the implementation of a wide spectrum of full search and reduced complexity search block matching algorithms is presented. Optimized efficiency for variable algorithm parameters is obtained by using a quadratic systolic array architecture with global accumulation, combined with a flexible meander-like data flow. Flexibility is further increased by cascadability and/or the possibility of parallel operation. Hardware overhead for particular algorithmic requirements, such as variable pixel resolution, subsampling with offset, and subpixel accuracy, is discussed in detail. A full-custom (CMOS) implementation for the architecture is described

Keywords

CMOS digital integrated circuits; VLSI; data flow computing; digital signal processing chips; search problems; systolic arrays; CMOS; VLSI architecture; block matching processor; flexible meander-like data flow; full search block matching algorithms; full-custom implementation; global accumulation; hardware overhead; offset; parallel operation; quadratic systolic array architecture; reduced complexity search block matching algorithms; subpixel accuracy; subsampling; variable algorithm parameters; variable pixel resolution; Bandwidth; Hardware; Motion estimation; Parallel processing; Sampling methods; Search methods; Signal processing algorithms; Systolic arrays; Transcoding; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.473554

Filename

473554