Title :
Redundancy identification and removal in combinational circuits
Author :
Menon, P.R. ; Ahuja, H. ; Harihara, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fDate :
5/1/1994 12:00:00 AM
Abstract :
Identification and removal of redundancy in digital circuits is important for improving their testability as well as reducing their area. This paper presents a method of identifying and removing redundancy in combinational circuits by analyzing circuit structure. Experimental results indicate that the method is quite efficient in execution time, but may not identify all undetectable faults. It is expected to be suitable for integration into a logic synthesis system. It can also be used as a preprocessor for a test pattern generation program or for a test pattern generation based redundancy removal program
Keywords :
combinatorial circuits; logic CAD; logic testing; redundancy; C language implementation; circuit structure analysis; combinational circuits; execution time; logic synthesis system; preprocessor; redundancy identification; redundancy removal; test pattern generation based redundancy removal program; test pattern generation program; testability; undetectable fault identification; Circuit analysis; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Digital circuits; Fault diagnosis; Logic; Redundancy; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
