Title :
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine
Author :
Kwanho Kim ; Seungjin Lee ; Joo-Young Kim ; Minsu Kim ; Hoi-Jun Yoo
Author_Institution :
Div. of Electr. Eng., Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon
Abstract :
A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit main processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The 36 mm2 chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mum 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V.
Keywords :
CMOS integrated circuits; SRAM chips; biomedical electronics; medical image processing; network-on-chip; object recognition; 2D shift register array; CMOS technology; DMA-like external interface; SRAM; adaptive switching; bio-inspired visual attention engine; bit rate 76.8 Mbit/s; cellular neural network based visual attention engine; image processing; matching accelerator; network-on-chip based parallel processor; object recognition; packet-based power management; power 583 mW; single-instruction multiple-data; size 0.13 mum; storage capacity 226 Kbit; voltage 1.2 V; CMOS technology; Cellular neural networks; Clustering algorithms; Energy management; Engines; Image processing; Network-on-a-chip; Object recognition; Packet switching; Shift registers; Matching accelerator; network-on-chip (NoC); object recognition; parallel processor; processing element clusters; visual attention engine;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2007157
