Title :
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate
Author :
Li, Yan ; Lee, Seungpil ; Fong, Yupin ; Pan, Feng ; Kuo, Tien-Chien ; Park, J. ; Samaddar, Tapan ; Nguyen, Hao Thai ; Mui, Man L. ; Htoo, Khin ; Kamei, Teruhiko ; Higashitani, Masaaki ; Yero, Emilio ; Kwon, Gyuwan ; Kliza, Phil ; Wan, Jun ; Kaneko, Tetsuy
Author_Institution :
NAND Design Dept., SanDisk Corp., Milpitas, CA
Abstract :
A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.
Keywords :
CMOS memory circuits; NAND circuits; flash memories; 3-bit per cell chip; CMOS technology; NAND flash memory; X3 chip; all-bitline architecture; bit rate 8 Mbit/s; cache program algorithm; cell source line noise; size 56 nm; storage capacity 16 Gbit; write performance; CMOS technology; Costs; Digital audio players; Energy consumption; Flash memory; Iris; Noise cancellation; Solid state circuits; Throughput; Tunneling; 3-bit per cell; 56nm; ABL architecture; NAND; X3 chip; all bitline; bitline control; cache program; flash memory; full sequence; source noise cancellation; wordline control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2007154
