• DocumentCode
    1055756
  • Title

    Current-gain enhancement in lateral p-n-p transistors by an optimized gap in the n+buried layer

  • Author

    Bhat, K.N. ; Achuthan, M.K.

  • Author_Institution
    Indian Institute of Technology, Madras, India
  • Volume
    24
  • Issue
    3
  • fYear
    1977
  • fDate
    3/1/1977 12:00:00 AM
  • Firstpage
    205
  • Lastpage
    214
  • Abstract
    A two-dimensional electrolytic tank analog study simulating volume recombination in the base region of lateral p-n-p transistors is presented. The effect of an n+buried layer is studied and it is found that a proper gap in this layer gives rise to a lateral transistor with common-emitter current-gain factor higher than that which can be achieved if the n+buried layer extends throughout the region below the transistor. This result is found to be true for various combinations of base geometry and minority carrier lifetimes which have been simulated. The analysis of the high-frequency performance shows that the gain-bandwidth product of the lateral p-n-p transistor is also maximized by providing an optimum gap in the buried layer.
  • Keywords
    Charge carrier lifetime; Epitaxial growth; Geometry; Helium; Iron; Monolithic integrated circuits; P-n junctions; Performance analysis; Solid modeling; Substrates;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1977.18710
  • Filename
    1478902