Title :
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
Author :
Ginsburg, Brian P. ; Chandrakasan, Anantha P.
Author_Institution :
MIT, Cambridge, MA
Abstract :
Ultra-wideband radio requires Nyquist sampling rates of at least 500 MS/s with low resolutions. While flash is the traditional choice for these specifications, a comparative energy model is used to show the potential energy savings of the time-interleaved successive approximation register architecture, which requires only a linear number of comparisons versus exponential for flash. A dual 500-MS/s, 5-bit ADC chip is implemented in a 0.18-mum CMOS process, with both ADCs synchronized for use in an I/Q UWB receiver. Each ADC uses a 6-way time-interleaved SAR topology with full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500-MS/s operation with 7.8 mW power consumption. The output resolution is adjustable down to the 1-bit level for additional power savings
Keywords :
CMOS integrated circuits; analogue-digital conversion; preamplifiers; radio receivers; ultra wideband communication; 0.18 micron; 5 bit; 7.8 mW; CMOS process; Nyquist sampling rates; comparator preamplifiers; dual time-interleaved analog-to-digital converter; duty cycling; self-timed bit-cycling; successive approximation register ADC; ultra-wideband communication; ultra-wideband radio; ultra-wideband receiver; CMOS logic circuits; CMOS process; Energy resolution; Potential energy; Receivers; Registers; Sampling methods; Semiconductor device modeling; Topology; Ultra wideband technology; ADC; CMOS; analog-to-digital conversion; scaleable; successive approximation register; ultra-wideband communication;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.889372
