Title :
A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop
Author :
Kao, Shao-Ku ; Chen, Bo-Jiun ; Liu, Shen-Iuan
Author_Institution :
Nat. Taiwan Univ., Taipei
fDate :
7/1/2007 12:00:00 AM
Abstract :
An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks.
Keywords :
UHF circuits; VHF circuits; delay lock loops; detector circuits; BTDC; all-digital DLL; all-digital delay-locked loop; binary time-to-digital converter; dynamic frequency detector; frequency 62.5 MHz to 625 MHz; Clocks; Counting circuits; Delay effects; Design for disassembly; Detectors; Frequency; Hardware; Jitter; Switches; Tracking loops; Delay-locked loop (DLL); lock detector; time-to-digital converter(TDC);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2007.895326
