DocumentCode
1056329
Title
High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation
Author
Meher, Pramod K. ; Patra, Jagdish C. ; Swamy, M.N.S.
Author_Institution
Nanyang Technol. Univ., Nanyang Avenue
Volume
54
Issue
7
fYear
2007
fDate
7/1/2007 12:00:00 AM
Firstpage
606
Lastpage
610
Abstract
A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures.
Keywords
VLSI; discrete Hartley transforms; distributed arithmetic; systolic arrays; N-point discrete Hartley transform; convolutional formulation; direct-memory-based implementation; distributed arithmetic-based implementation; hardware complexity; high-throughput memory-based architecture; memory-based systolic arrays; pipelined realization; Computer architecture; Convolution; Convolutional codes; Discrete Fourier transforms; Discrete transforms; Kernel; Memory architecture; Systolic arrays; Table lookup; Very large scale integration; Discrete Hartley transform (DHT); VLSI; systolic array;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2007.894407
Filename
4273643
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