Title :
A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
Author :
Yang, Rong-Jyi ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; 0.18 micron; 1.5 ps; 1.8 V; 12 ps; 12.6 mW; 40 to 550 MHz; CMOS technology; balanced edge combiner; closed-loop operation; duty cycle; fast-locking property; harmonic lock; harmonic-free all-digital delay-locked loop; synchronous clock; variable SAR algorithm; variable successive approximation register-controlled algorithm; Added delay; Approximation algorithms; CMOS technology; Clocks; Counting circuits; Delay lines; Frequency; Hardware; Jitter; Registers; ADDLL; DCC; delay-locked loop (DLL); edge combine; harmonic lock; successive approximation register (SAR); variable successive approximation register (VSAR);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.889381
